Semiconductor chips often need to have a unique identification (or identifier) marker. The identifier can be used to (i) restrict or allow access to content or services, (ii) track chip location or movement, (iii) determine a particular lot and wafer information for failure analysis, and (iv) encrypt or decrypt secure content. The first three examples are used where the chip provides an identity in response to a query. The identifier is sometimes referred to as an ID. Requesting an ID of a chip is called authentication. The last is an example where the chip uses an identifier to encrypt or decrypt a message and does not share the identifier with the requesters. The identifier in such an implementation is sometimes called a key. In both cases the identifier is a string of bits.
A good identifier should (i) be unique, or have a near-zero probability that another chip exists with the same identifier, and (ii) be invariant to temperature, voltage, noise, age, and any other parameters that can be altered. Specifically, for a good identifier every time the identifier is requested, the value generated should be the same.
An identifier can be a random or pseudo random number, an assigned number, or a mapping of carriers through the assembly-test operation. An identifier can be placed on the chip by laser trimming, bar coding, ink marking, or programming an EPROM or nonvolatile memory (as discussed in S. Runyon, “Startup points way to IC Fingerprints,” EE Times, February 2000.). However, such techniques use expensive machinery and/or implement additional processing and/or programming steps. Additionally, such techniques yield an identifier that may (i) not be electronically readable, (ii) be alterable, and/or (iii) be forgeable.
An identifier can be derived from the mismatches that occur between fabricated transistors. With proper circuitry such an identifier could be read electronically. Such an identifier is almost impossible to alter or forge. Finally, the same circuitry can be used on every chip to generate a unique identifier for each, eliminating expensive machinery and programming steps required for other identifiers.
As transistor dimensions are continually reduced with new fabrication process technologies, the variation in transistor behavior increases. Threshold voltage Vt for a given transistor (i.e., approximately the voltage at which a conducting channel forms beneath the gate) is a random variable approximately Gaussian with μVt and σVt. The generally accepted Pelgrom's model states that the standard deviation of the threshold voltage (σVt), increases as transistor dimensions decrease, as shown by the following equation EQ1:
                              σ          ⁢                                          ⁢          Vt                =                  K                      LxW                                              EQ        ⁢                                  ⁢        1            K is an empirically determined value and L and W are transistor length and width, respectively. Therefore, with each subsequent improvement in process technology, the specific threshold voltage Vt for a given transistor is becoming less controllable, as shown in FIG. 1. Consequently, two fabricated transistors that are designed to have identical Vt values most likely do not.
The basic idea to use Vt mismatch to generate an identifier is to fabricate an array of minimum-sized transistors (because they are most susceptible to process variation) and measure or detect the Vt mismatches. A company SiiDTech, based in Hillsboro, Oreg., in partial collaboration with, and licensed by, LSI Corporation, manufactures such a system.
Referring to FIG. 2, such a system 50 is shown. The system 50 is shown with a sequencer circuit 52, an input circuit 54, a transistor array 56, an auto-zeroing comparator 58, and an analog bias circuit 60. The transistor array 56 is a two-dimensional array of 224 field-effect biased transistor pairs. Switching circuitry is implemented to sequentially select the outputs of one of the pairs to feed to the auto-zeroing comparator 58 (see (i) K. Lofstrom, R. Daasch, and D. Taylor, “IC identification circuit using device mismatch,” IEEE Int. Solid-State Circuits Conf., 2000 and (ii) K. Lofstrom, D. Castaneda, B. Graff, and A. Cabbibo, “ICID,—tracing individual die from wafer test through end-of-life,” 10th Annual Int. Mixed-Signals Testing Workshop, pp. 20-28, June 2004.). The auto-zeroing comparator 58 presents either a logic 0 or a logic 1, depending on the voltage threshold Vt mismatch in the selected transistor pair. The system 50 was fabricated in a 0.13 μm process technology and yielded unique identifiers with 1-5% of the 224 bits being unpredictable.
To generate a device ID, where approximate matching can be used, the above system performs fairly well. However, to generate a key suitable for use in cryptography, where a match in every bit of the key is needed, the system 50 will not work due to the accuracy limitations described. In particular, the system 50 uses the auto-zeroing comparator 58 to detect the Vt mismatch between a pair of transistors of the array 56. The auto-zeroing (or calibrating) comparator 58, as well as the transistor cell array 56, relies on analog signals from the analog bias circuit 60.
It would be desirable to implement a system for generating an identifier that is unique, resilient, predictable and accurate enough to be usable in authentication and/or encryption systems.